The GDDR6 Controller IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The GDDR6 Controller IIP can be implemented in any technology.
The GDDR6 Controller IIP core supports the protocol standard JESD250, JESD250A and JESD250B specification with version 3.11 and is compatible with DFI-version 4.0 or 5.0 specification compliant. GDDR6 controller IIP also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXILite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.
The GDDR6 Controller IIP is delivered in Verilog RTL that GDDR6 be implemented in an ASIC or FPGA. The GDDR6 Controller IIP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.